1. Field of the Invention
This invention relates generally to logic signal storage and transmission circuits, and more particularly to a logic circuit to control complementary signal propagation between a pair of circuit blocks.
2. Description of the Background Art
A full adder is known as one of typical logic circuits. The full adder is a circuit which carries out adding operation of a digital signal corresponding to inputted addend and a digital signal corresponding to augend in consideration of carry, and outputs a digital signal corresponding to the sum thereof. The full adder receives a carry signal representing the presence or absence of carry. This full adder is employed in an integer multiplier constituting, for example, a floating point multiplier and serves as an important circuit portion for determining an operation speed of the floating point multiplier.
FIG. 9 is a schematic block diagram showing a configuration of the integer multiplier. Referring to this figure, multiplicand X and multiplier Y are inputted to a full adder array 80 through input circuit portions 81 and 82, respectively, in this integer multiplier. The full adder array 80, comprising a large number of full adders arranged in matrix, evaluates partial products of the multiplicand X and the multiplier Y. The partial products evaluated in the full adder array 80 are inputted through a latch circuit 83 to a full adder 84. This full adder 84 adds all the partial products inputted through the latch circuit 83 and obtains the product X x Y of the multiplicand X and the multiplier Y. The final multiplication result X x Y obtained in the full adder 84 is outputted through an output circuit 85.
In recent years, it is made public that a full adder disclosed in U.S. Pat. No. 4,870,609 is employed as the full adder constituting the full adder array 80 for evaluating the partial products in order to increase the operation speed of the above described integer multiplier.
FIG. 8 is a circuit diagram showing a configuration of an improved full adder disclosed in U.S. Pat. No. 4,870,609. Referring to FIG. 8, a feature of this full adder is in that all input signals and output signals are constituted by complementary signal pairs. That is, this full adder receives an augend signal A and its inverse signal A, an addend signal B and its inverse signal B, and a carry-in signal C.sub.in and its inverse signal C.sub.in and then evaluates the sum of the augend signal A and the addend signal B. The full adder then outputs the evaluated result as a sum signal S and its inverse signal S, and a carry-out signal CO and its inverse signal CO. Meanwhile, the conventional full adder receives an augend signal, an inverse signal of an addend signal, and a carry-in signal, in only either the non-inversion state or inversion state, evaluates the sum of the augend signal and the addend signal, and outputs this evaluated result as a sum signal and a carry-out signal in only either the non-inversion state or inversion state. In the foregoing conventional full adder, the inverse signal is formed in itself. Therefore, there is a problem in that the time taken to produce the inverse signal causes a delay in the adding operation.
On the other hand, since the full adder of FIG. 8 has such a configuration described above as to receive a complementary signal pair as its input, an effect is provided whereby the inverse signal does not need to be formed in the full adder and the full adder operation can be performed at a high speed. When this full adder different from the conventional one is employed for the full adder array 80 and the full adder 84 at the final stage in FIG. 9, each output of the full adder 80 becomes a complementary signal pair. Therefore, the latch circuit 83, provided between the full adder array 80 and the full adder 84 at the final stage, is required, if necessary, to hold the complementary signal pair and rapidly transmit the pair to the full adder 84 at the succeeding stage. Since the above described operation employing the complementary signal pair, in general, involves a risk that signal lines twice those in the conventional are required, it is mainly applied to a data execution unit of a CPU(Central Processing Unit) or to a circuit portion which requires a very high speed operation such as the multiplier described above. Therefore, the latch circuit included in this circuit portion need function to more rapidly transmit the complementary signal pairs to the succeeding stage than in the conventional.
FIG. 5 is a circuit diagram of one example of a conventional latch circuit. Referring to FIG. 5, the latch circuit comprises a data amplifying inverter 1 for amplifying an input data signal D (a digital signal of the potential level, logical high (the "H" level) or logical low (the "L" level), a data holding portion 29d for holding the input data signal D as data, and data amplifying inverters 3 and 4 for amplifying the data held by the data holding portion 29d and outputting the data to a circuit in the succeeding stage as output data signals Q and Q which are complementary to each other.
The data holding portion 29d comprises an input terminal 5, output terminals 7 and 8, a transmission gate 26 having a parallel connection of a P channel MOS transistor and an N channel MOS transistor, write control terminals 24 and 25 to be supplied with a complementary signal pair T and T for controlling ON/OFF of the transmission gate 26, and data holding inverters 22 and 23 for holding data inputted from the input terminal 5. The input terminal of the data holding inverter 22 is connected to the output terminal of the data holding inverter 23, while the output terminal of the data holding inverter 22 is connected to the input terminal of the data holding inverter 23. A connecting point of the output terminal of the inverter 22 and the input terminal of the inverter 23 is connected to the output terminal .theta.. Further, the input terminal 5 is connected to a connecting point (node i) of the input terminal of the inverter 22 and the output terminal of the inverter 23 via the transmission gate 26. A connecting point (node j) of the output terminal of the inverter 22 and the input terminal of the inverter 23 is connected to the output terminal 8. The write control terminals 24 and 25 are respectively connected to the gates of the N channel MOS transistor and P channel MOS transistor constituting the transmission gate 26.
The output terminal of the inverter 1 is connected to the input terminal 5 of the data holding portion 29d, and the input terminals of the inverter 3 and 4 are respectively connected to the output terminals 7 and 8 of the data holding portion 29d.
The operation of this circuit will be described hereinafter.
When potential levels of "H" and "L" are respectively applied to the write control terminals 24 and 25 as the signals T and T, the N channel MOS transistor and P channel MOS transistor constituting the transmission gate 26 are turned on, so that the transmission gate 26 is turned on. Meanwhile, the input data signal D to be written is inverted and amplified by the inverter 1 and transmitted to the input terminal 5. As a result, an inverted signal D of the input data signal transmitted to the input terminal 5 is transmitted to the input terminal of the inverter 22. The data signal transmitted to the input terminal of the inverter 22 is inverted by the inverter 22 and further inputted to the inverter 23. That is, the potential levels on the nodes i and j are determined by the input data signal D. This is called a data write-in state. If the input data signal written as above is held not to change responsive to a signal inputted later to the input terminal 5, the potential levels of the signals T and T applied to the write control terminals 24 and 25 are respectively inverted to be the "L" level and the "H" level. Accordingly, the transmission gate 26 is turned off, and further, the signal inputted to the input terminal 5 is not transmitted to the input terminal of the inverter 22. Meanwhile, the output of inverter 23 is fed back to the input terminal of the inverter 22. Therefore, the potential level on the node i is kept at the level in the write-in state responsive to the output of the inverter 23. In addition, the potential level on the node j is also kept at the level of the write-in state. That is, the input data signal inputted in advance is held at the connecting point of the inverters 22 and 23. This is called a data holding state.
As mentioned above, switching on/off the transmission gate 26 allows the switching between the data write-in state and the data holding state. The input data signal is derived from the output terminals 7 and 8. In other words, a signal to which the input data signal D is inverted and amplified by the inverter 1 is derived from the output terminal 7, and a signal inverted from this derived signal is derived from the output terminal 8. The signals of the complementary signal pair derived as above are respectively inverted and amplified by the inverters 3 and 4 and inputted to the adder in the succeeding stage.
When the data held by the inverters 22 and 23 is rewritten, the write control terminals 24 and 25 are supplied with the same signal as in the data write-in state, so that the transmission gate 26 is turned on and a data signal to be newly written is inputted to the inverter 1. Furthermore, if this newly written data is to be held, the same signal as in the data holding state is applied to the write control terminals 24 and 25.
A description will now be given on the relationship of "current handling capabilities" among the inverters 1, 22 and 23. The current handling capability of the transistor means the amount of current that the inverter is capable of carrying from the power supply to ground. As this amount of current increases, that is, as ON resistance of the transistor constituting the inverter increases, the current handling capability of the inverter increases. The current handling capability of the inverter 23 is lower than that of the inverter 22. This is possible because the inverter 23 is reliably operated responsive to the output of the inverter 22. Further, adjustments of the current handling capabilities of the inverters 1 and 23 are also required because such a case should be considered that the input data signal which is held is rewritten in response to the inverted signal thereof, i.e. a new input data signal. In this case, the potential level on the node i held by the output of the inverter 23 is opposite to the potential level transmitted to the input terminal 5 by the inverter 1 which received the new input data signal. Therefore, if the current handling capability of the inverter 23 is higher than that of the inverter 1, the potential level on the node i is hard to change with the output of the inverter 1. Accordingly, the potential on the node j is also hard to change with the input of the new data signal. That is to say, a problem arises that the new input data signal takes a long time to be written in the data holding portion 29d, or the correct writing may not be carried out. In order to eliminate this problem, the current handling capabilities of the inverters 1 and 23 should also be adjusted to each other. Therefore, the current handling capabilities of the inverters 1, 22 and 23 are adjusted to one another.
The conventional latch circuit for outputting complementary data signal pairs is configured as described above and involves such problems as follows.
FIG. 6 shows the conventional latch circuit shown in FIG. 5 in which the inverters 1 and 23 are shown in further detail. Referring to the figure, the inverter 1 comprises a series connection of a P channel MOS transistor Q1 and an N channel MOS transistor Q2, which is provided between high and low voltage sources 27 and 28. Similarly, the inverter 23 comprises a series connection of a P channel MOS transistor Q3 and an N channel MOS transistor Q4, which is provided between the high and low voltage sources 27 and 28.
FIG. 7 is a graph showing the relationship between the potentials on the nodes i and j in the latch circuits shown in FIGS. 5 and 6. In these figures, the abscissa designates a potential V.sub.i on the node i, and the ordinate designates a potential V.sub.j on the node j. Disadvantages involved in the conventional latch circuit will now be described with reference to FIGS. 6 and 7.
Assuming that the potential level on the node i is kept at the "L" level by the inverters 22 and 23 in the data holding state, the output potential level of the inverter 22 attains the "H" level, that is, the potential level on the node j attains the "H" level responsive to the potential level "L" on the node i. Furthermore, the transistor Q4 in the inverter 23 is turned on responsive to the potential level "H" on the node j. Accordingly, the output potential level of the inverter 23 goes to the "L" level, and the potential level on the node i is kept at the "L" level. Such a case is considered that the described data holding state turns to the data write-in state, so that the transmission gate 26 is turned on. At this time, if the potential level of the input data signal D inputted to the inverter 1 is at the "L" level, the transistor Q1 is turned on. Meanwhile, the transmission gate 26 is on, and the transistor Q4 constituting the inverter 23 is also on. Therefore, a current flows from the high voltage source 27 through the transistors Q1 and Q4 to the low voltage source 28. Accordingly, the potential level on the node i is determined by the ratio of ON resistance values of the transistor Q1 to the transistor Q4. Thus, if the resistance value of the transistor Q4 is set larger than that of the transistor Q1, since the amount of current flowing though the transistor Q4 is smaller than the current flowing through the transistor Q1, a high potential that the transistor Q1 supplies from the high voltage source 27 to the node i is hard to be lowered by the transistor Q4 which is rendered conductive in response to the potential on the node j, when the potential level of the input data signal D goes to the "L" level. Accordingly, the potential level on the node i goes rapidly to the "H" level, and thus the output potential level of the inverter 22 goes to the "L" level rapidly. Referring to FIG. 7, the potential V.sub.j on the node j undergoes a complementary change with the potential V.sub.i on the node i. Therefore, the rapid change of the potential V.sub.i on the node i from the "L" level to the "H" level means that the input data signal D is transmitted rapidly to the output terminals 7 and 8. However, when the potential level of the input data signal D attains the "H" level in the write-in state, the transistor Q2 comprised in the inverter 1 is turned on so as to transmit the potential level "L" level of the low voltage source 28 to the node i. Finally, the potential level on the node i goes to the "L" level while the potential level on the node j goes to the "H" level, and thus the transistor Q4 comprised in the inverter 23 should be turned on. Namely, the larger the current handling capability of the transistor Q4 is, the faster the input data signal D is transmitted to the output terminals 7 and 8. However, the current handling capability of the transistor Q4 decreases according as ON resistance value of the transistor Q4 increases. That is, the potential level on the node i slowly goes to the "L" level. In addition, the potential level on the node j also goes slowly to the "H" level. It means that the transmission rate of the input data signal D decreases when its potential level is in the "H" level.
On the other hand, assuming that the potential level on the node i is kept at the "H" level by the inverters 22 and 23 in the data holding state, the output potential level of the inverter 22 attains the "L" level, that is, the potential level on the node j attains the "L" level responsive to the potential level "H" on the node i. Furthermore, the transistor Q3 in the inverter 23 is turned on responsive to the potential level "L" on the node j. Accordingly, the output potential level of the inverter 23 goes to the "H" level, and the potential level on the node i is kept at the "H" level. Such a case is considered that the described data holding state turns to the data write-in state, so that the transmission gate 26 is turned on. At this time, if the potential level of the input data signal D inputted to the inverter 1 is at the "H" level, the transistor Q2 is turned on. Meanwhile, the transmission gate 26 is on, and the transistor Q3 constituting the inverter 23 is also on. Therefore, a current flows from the high voltage source 27 through the transistors Q3 and Q2 to the low voltage source 28. Accordingly, the potential level on the node i is determined by the ratio of ON resistance values of the transistor Q2 to the transistor Q3. Thus, if the resistance value of the transistor Q2 is set smaller than that of the transistor Q3, since the amount of current flowing through the transistor Q2 is larger than that flowing through the transistor Q3, a high potential that the transistor Q3 supplies from the high voltage source 27 to the node i is easily lowered by the transistor Q2, when the potential level of the input data signal D goes to the "L" level. Accordingly, the potential level on the node i goes rapidly to the "L" level, and thus the output potential level of the inverter 22 also goes to the "H" level rapidly. This means that the input data signal D is transmitted rapidly to the output terminals 7 and 8. However, when the potential level of the input data signal D attains the "L" level in the write-in state, the transistor Q1 comprised in the inverter 1 is turned on so as to transmit the potential level "H" level of the high voltage source 27 to the node i. Finally, the potential level on the node i goes to the "H" level while the potential level on the node j goes to the "L" level, and thus the transistor Q3 comprised in the inverter 23 should be turned on. Therefore, in this case, the potential level on the node i is easily raised to the "H" level by the transistor Q3 which renders conductive in response to the potential level on the node j. That is to say, the larger the current handling capability of the transistor Q3 is, the faster the input data signal D is transmitted to the output terminals 7 and 8. However, the current handling capability of the transistor Q3 decreases according as ON resistance value of the transistor Q3 increases. That is, if the resistance value of the transistor Q3 is set small, the potential level on the node i slowly goes to the "H" level. In addition, the potential level on the node j also goes slowly to the "L" level. This means that the transmission rate of the input data signal D decreases when its potential level is at the "L" level.
As described above, the faster the signal of the potential level "L" applied as the input data signal D is transmitted, the slower the signal of the potential level "H" is transmitted. On the other hand, the faster the signal of the potential level "H" is transmitted, the slower the signal of the potential level "L" is transmitted. That is to say, there is a limit to enhance the transmission rates of the both signals of the potential levels "L" and "H". As a result, there is a problem that the transmission rate of the input data signal is low in the conventional latch circuit.
Moreover, the following problem arises in the conventional latch circuit when a complementary signal pair, i.e. two output signals are inputted to a circuit at the same succeeding stage which requires the same simultaneously. That is to say, as seen from FIG. 5, one signal of the above described complementary signal pair is derived from the input terminal of the inverter 22, while the other is derived from the output terminal of the inverter 22. Therefore, a difference by a delay time in the inverter 22 occurs in the time required for transmitting each of the signals of the above described complementary signal pair to the circuit at the above described succeeding stage. This is undesirable because the circuit at the succeeding stage which requires two complementary signals at the same time causes a delay in transmission of the signals.